1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a non-volatile memory.
2. Description of Related Art
As the integration of semiconductor devices increases, the line width of the semiconductor devices must be reduced. However, as the size of the semiconductor devices, for example, memory devices decreases, a variety of problems is resulted. For example, as the line width of a memory device is reduced, the channel length between the source and the drain is correspondingly reduced, leading to the short channel effect.
Normally, a memory device integrates the memory cell arrays and the peripheral circuit elements onto a single chip. The peripheral circuit elements include high voltage (HV) devices and (LV) low voltage devices. The prior art method in forming such a memory device involves first forming a silicon oxide-silicon nitride-silicon oxide (ONO) composite structure in the memory array area, followed by forming the buried diffusion regions in the substrate adjacent to the ONO structure. The buried diffusion regions are formed by implanting dopants in the substrate. Thereafter, thermal oxidation processes are respectively performed to form the gate insulating layers for the high voltage devices and the low voltage devices in the peripheral circuit area.
According to the prior art fabrication method, subsequent to the formation of the buried diffusion regions in the memory array area, the high thermal budget processes, such as the fabrication of the thick gate insulating layers for the high voltage devices, can seriously affect the size of the buried diffusion region. In essence, the high temperature budget leads to an expansion of the buried diffusion regions. Consequently, the short channel effect is intensified. Further, the device may become defective.
To remedy the problems of diffusion junction expansion, a fabrication method has been proposed by forming thick gate insulating layer in the peripheral circuit area first, followed by the tunnel oxide in the memory array area and thin gate insulating layer in the peripheral circuit area. Buried diffusion regions are then formed by implanting ions in the substrate of the memory array area. Since the gate insulting layers are already formed in the peripheral circuit area, the size of the buried diffusion regions will not be affected by the high thermal budget processes. Thereafter, a silicon nitride layer and a top oxide layer are formed in both the memory array area and the peripheral circuit area to complete the formation of the ONO structure of the memory device. However, the silicon nitride layer and the top oxide layer in the peripheral circuit area have to be removed eventually. The removal of the silicon nitride layer and the top oxide layer, which requires the application of etchants such as hydrofluoric acid and hot phosphoric acid, may induce defects on the gate insulating layers underneath. Consequently, the quality of the devices in the peripheral circuit area is compromised. Defect control is especially critical for the LV gate insulating layer due to the delicate nature of the LV devices.